The next generation AMD processor microarchitecture known as Zen 4, which will underpin the 4th Gen AMD EPYC (Genoa) server processors, will include support for 512-bit AVX instruction sets. This is indicated by a slide, according to the source, borrowed from the official presentation.
If you believe the illustration, Genoa processors work in dual-processor configurations, will have “more than” 64 cores, each of which will be able to execute two streams of instructions at the same time. They will implement 52-bit real and 57-bit virtual addressing. In addition to support for AVX3-512, first mentioned in the AMD microarchitecture description, the processors will support BFloat16 and “other ISA extensions.”
It is not yet clear what specific AVX3-512 instructions are supported, and whether they will be equally available in Zen 4 client implementations.
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