Applied Materials has introduced a new way to make internal connections in logic ICs that can be scaled to 3nm and beyond.
With the development of ever more subtle norms, reducing the size improves the characteristics of the transistor, but increases the resistance of the internal connections, since it is inversely proportional to their cross section. This reduces performance and increases the power consumption of the chips. Without a breakthrough in materials science, the resistance of internal connections would increase by a factor of 10 when going from 7nm to 3nm norms, negating the benefits of transistor scaling.
To remedy this, Applied Materials developed an integrated manufacturing solution called Endura Copper Barrier Seed IMS. It performs seven different technological processes in one system under high vacuum conditions: surface preparation, surface modification at the atomic level, selective atomic layer deposition (ALD), metrological control, vacuum deposition (PVD), chemical vapor deposition (CVD) and copper reflow. The use of selective ALD instead of conformal ALD eliminates the high resistivity barrier. The solution also includes a copper reflow stage, in which narrow gaps are filled by capillary action. As stated, the reduction in the resistance of through contacts due to the application of the new technology reaches 50%.
It remains to add that Endura Copper Barrier Seed IMS is already in use by leading Applied Materials customers.
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