The JEDEC Solid State Technology Association, a microelectronics industry standard, has announced the publication of the JESD79-5A DDR5 SDRAM standard. This update to the JEDEC DDR5 SDRAM standard includes features designed to improve reliability and performance in a wide range of applications, including client systems and high-performance servers. The JESD79-5A standard is already available for download from the JEDEC website.
Additional features designed to meet industry demand for improved system reliability include new error detection and correction capabilities. In addition, the JESD79-5A extends timing detection and DDR5 data rates to 6400 MT / s for DRAM core timings and 5600 MT / s for I / O timing. The nomenclature of kernel timing parameters and their corresponding definitions have been redesigned to comply with the upcoming JEDEC JESD400-5 DDR5 Serial Presence Detect (SPD) Contents V1.0 standard.
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