Synopsys last week unveiled the industry’s first full suite of IP cores for PCIe 6.0. It includes a controller, a physical layer interface (PHY), and a verification tool. Having the kit will allow SoC developers to start including support for the next generation interface in their projects.
The IP core of the Synopsys DesignWare for PCIe 6.0 controller is based on the widely used and well-proven DesignWare for PCIe 5.0 core. Of course, the new core supports the innovations added in PCIe 6.0, including double data rate (up to 64 GT / s), four-level pulse amplitude modulation (PAM4), FLIT mode, and L0p power-down state. The physical layer interface is designed for 5 nm fabrication. The combination of “unique analog and DSP technologies” has reduced power consumption by 20%. According to Synopsys, the proposed IP solution “meets the growing demands for latency, bandwidth and energy efficiency in high performance computing, artificial intelligence and storage.”
The DesignWare controller and PHY are slated to be available in the third quarter of 2021, and an IP core for PCIe 6.0 verification is already available.
Recall that in November last year the PCIe 6.0 specification version 0.7 was received by members of the PCI-SIG association, and its final version should be ready this year.
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