In early December 2022, Wikichip reported that TSMC’s 3nm process showed little to no improvement in density over the same company’s previous 5nm node in SRAM (Static Random Access Memory) density. The publication asked only one simple question – have we just witnessed the death of SRAM? At least according to Wikichip, “historical scaling is officially dead.”
And in fact, this idea has enormous implications for the entire technology industry – the consequences will be felt in the PC market and in segments of other types of electronics for many years to come. But you are probably now asking yourself what all this means and whether it is worth worrying about this issue. To understand how the “death of SRAM” will affect the PC and how chip manufacturers will deal with it, we need to talk a little about process technology, Moore’s law and cache memory.
Moore’s law died gradually
It’s safe to say that Moore’s Law is the real benchmark for success in the semiconductor industry. It says that new chips should have twice as many transistors as two-year-old chips. Intel, AMD, and other chip designers want to make sure they’re keeping up with Moore’s Law, because failing to keep up with the times means losing a technological edge to competitors.
Since processors must maintain adequate dimensions, the only sure way to increase the number of transistors is to reduce their physical size and pack them more tightly. The manufacturing process is how a semiconductor manufacturer makes a chip, and the manufacturing process is usually determined by the size of the transistor, so smaller is better. Switching to the latest manufacturing process has always been a reliable way to increase the number of transistors and therefore the performance of the chip – for decades the industry has been able to use this tool, meeting all expectations.
Unfortunately, Moore’s law has been dying for many years, since about 2010, when the industry moved to 32nm process technology. When manufacturers tried to go further, they literally hit a brick wall. The fact is that all major manufacturers, from TSMC to Samsung to GlobalFoundries, have been actively working on creating something smaller than 32 nanometers. Eventually, new technologies were developed to take things further in this direction, but transistors can no longer be scaled down as they used to be. Now the process name doesn’t reflect how compact a transistor really is, and new processors no longer show the increase in packing density that the industry is accustomed to.
So what happened to TSMC’s 3nm process? The fact is that in a typical processor there are two main types of transistors – for logic and for SRAM (or cache memory). For some time, logic has been noticeably easier to compress than cache, because the cache is already very dense, but now for the first time in years, we see that TSMC’s manufacturing facilities cannot compress logic in a new workflow. Accordingly, a variant of the 3nm process with significantly higher cache density is expected in the near future, but TSMC is certainly in a very uncomfortable situation where scaling becomes too small. And other manufacturers may soon face the same problem.
But the problem is not only the inability to increase the amount of cache memory without taking up more space. Processors are not dimensionless, and any space occupied by cache memory is space that cannot be used for logic or transistors, which result in a direct performance boost. At the same time, processors with more cores and other advanced features need more cache to avoid memory bottlenecks. And while logic density continues to increase with each new process, it may not be enough to make up for SRAM’s lack of scaling, which could be the death blow to Moore’s Law.
How the industry can solve the SRAM problem
There are three variables to consider – the size of new processors is limited, processors require cache memory, and new manufacturing processes will no longer noticeably reduce the physical size of cache memory (if they manage to reduce these sizes even a little in the future). And while it is possible to improve processor performance through architectural improvements and higher clock speeds, adding more transistors has always been the easiest and most effective way to increase performance gains between generations. And to overcome this problem, you need to change one of the three key variables.
And, as it turned out, there has long been a wonderful and, most importantly, a working solution to the SRAM problem – chiplets. This is a technology that AMD has been using since 2019 for its desktop and server processors. The chipset design uses several silicon elements (or dies), each of which perform one or more functions – for example, some elements can only contain cores. This is contrary to the monolithic design, which implies that everything is on a single chip.
Chips really solve the physical size problem, which is a key reason why AMD has been able to keep up with Moore’s Law. After all, this law does not apply to density, but to the number of transistors. And thanks to this chiplet technology, AMD was able to create processors with a total die density of more than 1000 mm² – the production of such a central processing unit in an “all-on-one chip” format is probably simply impossible.
The most important thing AMD engineers have done to solve the cache problem is to put that memory on its own die. V-Cache inside the Ryzen 7 5800X3D processor and the memory chiplets in the RX 7000 series graphics cards are a visual demonstration of cache memory chipsets in action. It’s likely that AMD noticed the trouble in the market, since cache memory has been hard enough to compress for years, and decided to separate this memory from everything else in order to leave more room for larger chiplets with more cores.
For example, the main die size of the RX 7900 XTX is only 300 mm², which means that AMD has enough space to make a larger die if desired. However, chiplets are not the only way to solve the problem. NVIDIA’s CEO recently announced the death of Moore’s Law. The company itself relies solely on its AI technology to achieve greater performance without abandoning the monolithic design. NVIDIA’s latest architecture called Ada Lovelace is theoretically many times faster than the previous generation Ampere, thanks to features like DLSS 3.
However, of course, in the coming years we will see for sure whether the industry giants need to support Moore’s law or it’s time to come up with a new law that meets the technological features of the modern world.
Source: XDA Developers.
Source: Trash Box
Charles Grill is a tech-savvy writer with over 3 years of experience in the field. He writes on a variety of technology-related topics and has a strong focus on the latest advancements in the industry. He is connected with several online news websites and is currently contributing to a technology-focused platform.