AMD has revealed some technical details about 3D V-Cache technology, which allows existing processors to add large amounts of cache memory.
Recall that AMD has already shown a modified Ryzen 9 5900X, and processors with 3D V-Cache will appear on sale either at the end of this year or at the beginning of next.
So, the development of AMD is based on the TSMC SoIC packaging technology, which makes such expansion of crystals along the vertical axis possible. At the same time, not microprotrusions, as previously assumed, are used to connect the crystals to each other, but the TSV (Through Silicon Vias) technology, which IBM introduced back in 2007. It allows the components of the chips to be placed very close to each other.
True, to implement all these technologies, AMD had to literally turn the processor chiplets upside down and remove some of the silicon (AMD is talking about removing 95% of the die thickness). Only after that, the SRAM chip is attached to the upper part of the chiplet, which was previously the lower one, which acts as a cache memory expander.
This solution can significantly reduce the distance between the additional cache and the chiplet. More precisely, it is 1000 times less than if the cache was added not on top, but on the side of the main chip. This, in turn, has reduced power consumption, temperatures, and latency.
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